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the hitachi HM514280A/al are cmos dynamic ram organized as 262,144-word 18-bit. HM514280A/al have realized higher density, higher performance and various functions by employing 0.8 ? cmos process technology and some new cmos circuit design technologies. the HM514280A/al offer fast page mode as a high speed access mode. multiplexed address input permits the HM514280A/al to be packaged in standard 400- mil 40-pin plastic soj, standard 475-mil 40-pin plastic zip and standard 400-mil 44-pin plastic tsopii. features single 5 v (?0%) high speed access time: 70 ns/80 ns (max) low power dissipation active mode: 825 mw/770 mw (max) standby mode: 11 mw (max) 1.1 mw (max) (l-version) fast page mode capability 512 refresh cycles: 8 ms 128 ms (l-version) ? cas byte control 2 variations of refresh ras -only refresh cas -before- ras refresh battery back up operation (l-version) ordering information access type no. time package HM514280Aj-7 70 ns 400-mil 40-pin HM514280Aj-8 80 ns plastic soj (cp-40d) HM514280Az-7 70 ns 475-mil 40-pin HM514280Az-8 80 ns plastic zip (zp-40) HM514280Att-7 70 ns 400-mil 44-pin HM514280Att-8 80 ns plastic tsopii (ttp-44/40db) HM514280Alj-7 70 ns 400 mil 40-pin HM514280Alj-8 80 ns plastic soj (cp-40d) HM514280Alz-7 70 ns 475-mil 40-pin HM514280Alz-8 80 ns plastic zip (zp-40) HM514280Altt-7 70 ns 400 mil 44-pin HM514280Altt-8 80 ns plastic tsopii (ttp-44/40db) 1 HM514280A/al series 262,144-word 18-bit dynamic random access memory
pin arrangement pin description pin name function a0 a8 address input row address a0 ?a8 column address a0 ?a8 refresh address a0 ?a8 i/o0 ?i/o17 data-in/data-out ras row address strobe ucas , lcas column address strobe we read/write enable oe output enable v cc power (+5 v) v ss ground v i/o0 i/o1 i/o2 i/o3 v i/o4 i/o5 i/o6 i/o7 i/o8 nc we ras nc a0 a1 a2 a3 v cc cc cc v i/o17 i/o16 i/o15 i/o14 v i/o13 i/o12 i/o11 i/o10 i/o9 lcas ucas oe a8 a7 a6 a5 a4 v ss ss ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 (top view) HM514280Aj/alj series 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 cc i/o10 i/o12 v i/o15 i/o17 v i/o1 i/o3 i/o4 i/o6 i/o8 we nc a1 a3 v a5 a7 oe lcas ss i/o11 i/o13 i/o14 i/o16 v i/o0 i/o2 v i/o5 i/o7 nc ras a0 a2 v a4 a6 a8 ucas i/o9 ss ss cc cc (bottom view) HM514280Az/alz series v i/o0 i/o1 i/o2 i/o3 v i/o4 i/o5 i/o6 i/o7 i/o8 nc we ras nc a0 a1 a2 a3 v cc cc cc v i/o17 i/o16 i/o15 i/o14 v i/o13 i/o12 i/o11 i/o10 i/o9 lcas ucas oe a8 a7 a6 a5 a4 v ss ss ss 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23 HM514280Att/altt series (top view) 2 HM514280A/al series HM514280A/al series
block diagram 288 k memory array mat i/o bus & column decoder 288 k memory array mat 288 k memory array mat 288 k memory array mat 288 k memory array mat 288 k memory array mat 288 k memory array mat 288 k memory array mat i/o bus & column decoder peripheral circuit i/o bus & column decoder i/o bus & column decoder 288 k memory array mat i/o bus & column decoder 288 k memory array mat 288 k memory array mat 288 k memory array mat 288 k memory array mat 288 k memory array mat 288 k memory array mat 288 k memory array mat i/o bus & column decoder peripheral circuit i/o bus & column decoder i/o bus & column decoder row decoder row decoder row decoder row decoder row decoder row decoder row decoder row decoder selector selector selector selector peripheral circuit we ras ucas oe i/o14 buffer i/o15 buffer i/o16 buffer i/o17 buffer i/o0 buffer i/o1 buffer selector selector selector selector i/o2 buffer i/o3 buffer i/o4 buffer i/o14 i/o15 i/o16 i/o17 i/o0 i/o1 i/o2 i/o3 i/o4 address a0,a1,a2,a3 address a4,a5 a6,a7,a8 row decoder row decoder row decoder row decoder row decoder row decoder row decoder row decoder i/o5 buffer i/o5 i/o6 buffer i/o6 i/o7 buffer i/o7 i/o13 i/o12 i/o11 i/o10 i/o13 buffer i/o12 buffer i/o11 buffer i/o10 buffer lcas i/o9 i/o9 buffer i/o8 buffer i/o8 3 HM514280A/al series HM514280A/al series
truth table inputs i/o ras lcas ucas we oe i/o0 i/o8 i/o9 i/o17 operation h h h h h high-z high-z standby l h h h h high-z high-z refresh l l h h l dout high-z lower byte read l h l h l high-z dout upper byte read l l l h l dout dout word read l l h l h din don? care lower byte write l h l l h don? care din upper byte write l l l l h din din word write l l l h h high-z high-z h to l l h high-z high-z cbr refresh h to l h l high-z high-z h to l l l high-z high-z absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v t ?.0 to +7.0 v supply voltage relative to v ss v cc ?.0 to +7.0 v short circuit output current iout 50 ma power dissipation p t 1.0 w operating temperature topr 0 to +70 ? storage temperature tstg ?5 to +125 ? 4 HM514280A/al series HM514280A/al series
recommended dc operating conditions (ta = 0 to +70?) *2 parameter symbol min typ max unit note supply voltage v ss 000v v cc 4.5 5.0 5.5 v 1 input high voltagev ih 2.4 6.5 v 1 input low (i/o pin) v il ?.0 0.8 v 1 voltage (others) v il ?.0 0.8 v 1 notes: 1. all voltage referenced to v ss 2. the supply voltage with all v cc pins must be on the same level. the supply voltage with all v ss pins must be on the same level. dc characteristics (ta = 0 to +70?, v cc = 5 v 10%, v ss = 0 v) HM514280A/al -7 -8 parameter symbol min max min max unit test conditions notes operating current i cc1 150 140 ma ras cycling 1, 2 lcas or ucas cycling t rc = min standby current i cc2 2 2 ma ttl interface ras , lcas , ucas = v ih dout = high-z 1 1 ma cmos interface ras , lcas , ucas , we oe > v cc ?0.2 v dout = high-z standby current 200 200 ? cmos interface (l-version) ras , lcas , oe , we ucas > v cc ?0.2 v dout = high-z ras -only refresh i cc3 140 130 ma t rc = min 2 current standby current i cc5 ? ? ma ras = v ih 1 lcas or ucas = v il dout = enable cas -before- ras i cc6 140 130 ma t rc = min 25 refresh current 5 HM514280A/al series HM514280A/al series
dc characteristics (ta = 0 to +70?, v cc = 5 v 10%, v ss = 0 v) (cont) HM514280A/al -7 -8 parameter symbol min max min max unit test conditions notes fast page mode i cc7 130 120 ma t pc = min 1, 3 current battery back up i cc10 300 300 ? standby: cmos interface 4 current dout = high-z (standby with cbr refresh: t rc = 250 ? cbr refresh) t ras < 1 ?, lcas , (l-version) ucas = v il , we , oe = v ih input leakage current i li ?0 10 ?0 10 ? 0 v < vin < 6.5 v output leakage current i lo ?0 10 ?0 10 ? 0 v < vout < 6.5 v dout = disable output high voltage v oh 2.4 v cc 2.4 v cc v high iout = ?.0 ma output low voltage v ol 0 0.4 0 0.4 v low iout = 4.2 ma notes: 1. i cc depends on output load condition when the device is selected. i cc max is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. address can be changed once or less while lcas and ucas = v ih . 4. v ih > v cc ?0.2 v, 0 < v il < 0.2 v, address can be changed once or less while ras = v il . 5. all the v cc pins shall be supplied with the same voltage. and all the v ss pins shall be supplied with the same voltage. capacitance (ta = 25?, v cc = 5 v 10%) parameter symbol typ max unit notes input capacitance (address) c i1 5 pf 1 input capacitance (clocks) c i2 7 pf 1 output capacitance (data-in, data-out) c i/o 10 pf 1, 2 notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. lcas and ucas = v ih to disable dout 6 HM514280A/al series HM514280A/al series
ac characteristics (ta = 0 to +70?, v cc = 5 v 10%, v ss = 0 v) *1, *14, *15, *17, *18 test conditions read, write, read-modify-write and refresh cycles (common parameters) HM514280A/al -7 -8 parameter symbol min max min max unit notes random read or write cycle time t rc 130 150 ns ras precharge time t rp 50 60 ns ras pulse width t ras 70 10000 80 10000 ns cas pulse width t cas 20 10000 20 10000 ns 23 row address setup time t asr 00ns row address hold time t rah 10 10 ns column address setup time t asc 0 0 ns 19 column address hold time t cah 15 15 ns 19 ras to cas delay time t rcd 20 50 20 60 ns 8 ras to column address delay time t rad 15 35 15 40 ns 9 ras hold time t rsh 20 20 ns cas hold time t csh 70 80 ns cas to ras precharge time t crp 15 15 ns 20, 24 oe to din delay time t odd 20 20 ns oe delay time from din t dzo 00ns cas setup time from din t dzc 00ns transition time (rise and fall) t t 3 50 3 50 ns 7 refresh period t ref ? ? ms refresh period (l-version) t ref 128 128 ms input rise and fall times: 5 ns input timing reference levels: 0.8 v, 2.4 v output load: 2 ttl gate + c l (100 pf) (including scope and jig) 7 HM514280A/al series HM514280A/al series
read cycle HM514280A/al -7 -8 parameter symbol min max min max unit notes access time from ras t rac 70 80 ns 2, 3 access time from cas t cac 20 20 ns 3, 4, 13 access time from address t aa 35 40 ns 3, 5, 13 access time from oe t oac 20 20 ns 3, 23 read command setup time t rcs 0 0 ns 19 read command hold time to cas t rch 0 0 ns 16, 19 read command hold time to ras t rrh 0 0 ns 16 column address to ras lead time t ral 35 40 ns output buffer turn-off time t off1 0 15 0 15 ns 6 output buffer turn-off to oe t off2 0 15 0 15 ns 6 cas to din delay time t cdd 15 15 ns write cycle HM514280A/al -7 -8 parameter symbol min max min max unit notes write command setup time t wcs 0 0 ns 10, 19 write command hold time t wch 15 15 ns 19 write command pulse width t wp 10 10 ns write command to ras lead time t rwl 20 20 ns write command to cas lead time t cwl 20 20 ns 21 data-in setup time t ds 0 0 ns 11, 21 data-in hold time t dh 15 15 ns 11, 21 cas to oe delay time t cod 0 0 ns 23 8 HM514280A/al series HM514280A/al series
read-modify-write cycle HM514280A/al -7 -8 parameter symbol min max min max unit notes read-modify-write cycle time t rwc 180 200 ns ras to we delay time t rwd 95 105 ns 10 cas to we delay time t cwd 45 45 ns 10 column address to we delay time t awd 60 65 ns 10 oe hold time from we t oeh 20 20 ns refresh cycle HM514280A/al -7 -8 parameter symbol min max min max unit notes cas setup time ( cas -before- ras refresh cycle) t csr 10 10 ns 19 cas hold time ( cas -before- ras refresh cycle) t chr 10 10 ns 20 ras precharge to cas hold time t rpc 10 10 ns 19 cas precharge time in normal mode t cpn 10 10 ns 22 9 HM514280A/al series HM514280A/al series
fast page mode cycle HM514280A/al -7 -8 parameter symbol min max min max unit notes fast page mode cycle time t pc 45 50 ns fast page mode cas precharge time t cp 10 10 ns 22 fast page mode ras pulse width t rasc 100000 100000 ns 12 access time from cas precharge t acp 40 45 ns 3, 13, 20 ras hold time from cas precharge t rhcp 40 45 ns fast page mode read-modify-write cycle t cpw 65 70 ns cas precharge to we delay time fast page mode read-modify-write cycle time t pcm 95 100 ns notes: 1. ac measurements assume t t = 5 ns. 2. assumes that t rcd < t rcd (max) and t rad < t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 3. measured with a load circuit equivalent to 2 ttl loads and 100 pf. 4. assumes that t rcd > t rcd (max) and t rad < t rad (max). 5. assumes that t rcd < t rcd (max) and t rad > t rad (max). 6. t off (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih and v il . 8. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only, if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 9. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only, if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 10. t wcs , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only: if t wcs > t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t rwd > t rwd (min), t cwd > t cwd (min), t awd > t awd (min) and t cpw > t cpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. these parameters are referenced to cas leading edge in an early write cycle and to we leading edge in a delayed write or a read-modify-write cycle. 12. t rasc defines ras pulse width in fast page mode cycles. 13. access time is determined by the longer of t aa or t cac or t acp . 14. an initial pause of 100 ? is required after power up followed by a minimum of eight initialization cycles ( ras -only refresh cycle or cas -before- ras refresh cycle). if the internal refresh counter is used, a minimum of eight cas -before- ras refresh cycles is required. 15. in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device. 16. either t rch or t rrh must be satisfied for a read cycle. 10 HM514280A/al series HM514280A/al series
17. when both lcas and ucas go low at the same time, all 18-bits data are written into the device. lcas and ucas cannot be staggered within the same write/read cycles. 18. all the v cc and v ss pins shall be supplied with the same voltages. 19. t asc , t cah , t rcs , t rch , t wcs , t wch , t csr and t rpc are determined by the earlier falling edge of ucas or lcas . 20. t crp , t chr , t acp and t cpw are determined by the later rising edge of ucas or lcas . 21. t cwl , t dh, t ds and t chs should be satisfied by both ucas and lcas . 22. t cpn and t cp are determined by the time that both ucas and lcas are high. 23. when output buffers are enabled once, sustain the low impedance state until valid data is obtained. when output buffer is turned on and off within a very short time, generally it causes large v cc /v ss line noise, which causes to degrade v ih min/v il max level. 24. t crp is planned to be improved to match the standard dram specifications. 11 HM514280A/al series HM514280A/al series
notes concerning 2 cas control please do not separate the ucas / lcas operation timing intentionally. however skew between ucas / lcas are allowed under the following conditions. (1) each of the ucas / lcas should satisfy the timing specifications individually. (2) different operation mode for upper/lower byte is not allowed; such as following. (3) closely separated upper/lower byte control is not allowed. however when the condition (t cp < t ul ) is satisfied, fast page mode can be performed. ras ucas lcas we delayed write early write ras ucas lcas t ul 12 HM514280A/al series HM514280A/al series
timing waveforms *25 read cycle note 25. h or l (h: v ih (min v in v ih (max), l: v il (min) v in v il (max)) invalid dout ras address we dout t ras t rc t rp t csh t rcd t rsh t cas t ral t cah t rad t t asr rah t asc t rcs t rch t rrh t cac t off1 t aa t rac t t t crp row column dout din oe high-z dzc t high-z dzo t t oac t cdd t off2 t odd ucas lcas 13 HM514280A/al series HM514280A/al series
early write cycle ras address we din dout * t ras t rp t rc t csh t crp t rcd t rsh t cas t t t cah t asc t rah t asr row column t wcs t ds t dh din high-z t wch * oe : h or l ucas lcas 14 HM514280A/al series HM514280A/al series
delayed write cycle address ras we din dout t ras t rc t rp t csh t crp t rcd t rsh t cas t asr t rah t asc t cah row column t rcs t wp t rwl t cwl t ds t dh din t odd t off2 t t * do not enable dout during delayed write cycle. oe t dzc t dzo t oeh * ucas lcas t cod invalid dout* 15 HM514280A/al series HM514280A/al series
read-modify-write cycle din dout address ras t rwc t rp t crp t t t rcd t rad t asr t rah t cah t asc row column t cwd t rcs t awd t rwd t wp t cwl t rwl t ds t dh din t odd t aa t off2 t oeh t rac oe dout t dzo t oac high-z t dzc t cac we ucas lcas 16 HM514280A/al series HM514280A/al series
ras -only refresh cycle ras address dout * : h or l ** oe, we t rc t ras t rp t t t crp t rpc t crp t asr t rah row high-z refresh address : a0 ?a8 (ax0 ?ax8) ucas lcas 17 HM514280A/al series HM514280A/al series
cas -before- ras refresh cycle ras address dout t rc t rc t rp t ras** t rp t ras** t rp t rpc t t t cpn t csr t chr t cpn t csr t rpc t chr t crp t off1 high-z *we ucas lcas ** do not extend t 3 t max. untested self refresh mode may be activated and loss of data may be resulted (HM514280A/al). ras ras : h or l 18 HM514280A/al series HM514280A/al series
fast page mode read cycle ras address din dout t rasc t rp t t t csh t pc t rsh t crp t cas t cp t cas t cp t cas t rcd t asr t rah t asc t cah t asc t cah t cah row column column column t rac t rch t rrh t aa t cdd t odd high-z t rcs t rch t rcs t dzc t rcs t cdd oe t rhcp t rad t ral dout dout dout t cdd t odd t dzo t off2 t oac t oac t odd t dzo dzc t t off2 t oac t off1 t aa t cac t acp t dzo t acp t aa t cac t off1 t off1 t cac t high-z high-z t dzc t asc t rch off2 we ucas lcas 19 HM514280A/al series HM514280A/al series
fast page mode early write cycle ras address we din dout t rasc t rp t t t csh t pc t rsh t crp t cas t cp t cas t cp t cas t rcd t asr t rah t asc t cah t asc t cah t asc t cah row column column column t ds t dh t ds t dh t ds t dh din din din high-z t wcs t wch *oe : h or l t wch t wcs t wcs t wch ucas lcas 20 HM514280A/al series HM514280A/al series
fast page mode delayed write cycle ucas lcas din we address ras dout t rasc t rp t t t csh t pc t rsh t cas t rcd t cp t cas t cp t cas t crp t asr t rah t asc t cah t asc t cah t asc t cah row column column column t wp t rcs t rcs t cwl t t cwl t cwl t t ds t dh t ds t ds t dh din din din oe t odd t oeh t dh high-z t wp t rcs rwl wp 21 HM514280A/al series HM514280A/al series
fast page mode read-modify-write cycle din dout address ras t rasc t t cp t pcm t t t rcd t t cp t rad t asr t asc t t t rah t t cah t t cpw t t cpw t cwl t rwd t awd t awd t awd t cwd t t cwd t cwd t rcs t wp t t wp t ds t t dh t t ds t dzc t dh t odd t dh t cac t dzo t oeh t oeh t oeh t aa t din din din t rp t rwl t oac t odd t t odd t dzo t t t dzo aa t oe dout dout dout t cah t ds column column column row rac cwl high-z cac acp wp cwl cac t crp asc acp cah t asc rcs high-z high-z oac t dzc dzc rcs oac t off2 we ucas lcas t off2 t off2 22 HM514280A/al series HM514280A/al series

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